描述
开 本: 16开纸 张: 胶版纸包 装: 平装是否套装: 否国际标准书号ISBN: 9787030317667
编辑推荐
本书介绍应用集成电路设计的整体流程以及流程涉及的每个步骤，这些步骤之间的内在关系，以及如何使用工业化的实际的集成电路计算机辅助设计软件完成设计任务。本书的一个突出特点是使用一个实际的应用设计例子，有限响应滤波器的设计，引导读者走通设计的全部细节。这样一个设计实例使得读者获得**手的设计经验和使用工业化计算机辅助设计软件的知识。书中附带了这个设计案例的全部硬件描述语言代码以供参考。
内容简介
本书基于作者周电在美国大学十几年教授“现代应用集成电路设计”课程的手稿整理而成，主要内容包括应用集成电路设计流程、设计指标定义和规范、逻辑电路设计、物理设计、时间功耗性能分析及验证测试。读者需要有数字集成电路和硬件描述语言（VHDL）的基础知识。按照具体课程设置的要求，本书可用于一个学期的教学内容，包括应用集成电路设计流程、设计指标定义和规范、逻辑电路设计及物理设计。关于集成电路发展的前沿问题，本书在第7章和第8章中以研究课题为背影介绍了基础知识。
本书可作为电子和计算机工作专业的大学四年级或硕士研究生教材，也适于集成电路设计的专业人员参考阅读。
目 录
Preface
Chapter 1 Introduction
1.1 History of Integrated Circuits
1.2 Roadmap of IC Technology
1.3 ASIC
1.4 Design Flow
1.5 CAD Tools
1.6 AnASIC Design Project MSDAP
1.7 How to Use This Book
1.8 Summery
1.9 Problems
References
Chapter 2 VLSI Design Perspective and Flow
2.1 Introduction
2.2 VLSI Technology Trend
2.3 SoC
2.4 Methodology for Custom and Semi-custom IC Design
2.4.1 Gate array
2.4.2 Standard cell
2.4.3 FPGA
2.5 Design Domain and Perspective
2.6 Design Flow
2.7 Design Task
2.8 Summary
2.9 Problems
References
Chapter 3 Specification Development
3.1 Introduction
3.2 AnASIC Project MSDAP
3.3 An Overall View of the Specific Requirement
3.3.1 The required computation method by the MSDAP
3.3.2 Additional information for the specification
3.4 The System Setting
3.5 I/O Interface and Pins
3.5.1 Pins and their assignments
3.5.2 Signal format and waveform
3.6 Other Issues of the Specification
3.7 Summary
3.8 Problems
References
Chapter 4 Architecture Design
4.1 Introduction
4.2 Datapath Structure
4.2.1 Single processor sequential structure
4.2.2 Multi-processor parallel structure
4.3 Functional Blocks and IPs
4.3.1 IP core
4.3.2 Functional blocks in the MSDAP architecture
4.4 Time Budget and Scheduling
4.5 A Sample Architecture of the MSDAP Project
4.5.1 An architecture sample
4.5.2 Time budget justification of the proposed architecture
4.6 Summary
4.7 Problems
References
Chapter 5 Logic and Circuit Design
5.1 Introduction
5.2 Combinational Logics
5.2.1 Decoder
5.2.2 Encoder
5.2.3 Multiplexer
5.2.4 Arithmetic logic blocks
5.3 Sequential Logics
5.3.1 Latch and flip-flop
5.3.2 Shift register
5.3.3 Counter
5.3.4 FSM
5.4 Datapath
5.5 Asynchronous Circuit
5.6 Summery
5.7 Problems
References
Chapter 6 Physical Design
6.1 Introduction
6.2 Design Rules
6.3 Floorplan
6.4 Routing
6.4.1 Global routing
6.4.2 Local routing
6.5 Physical Layout Verification
6.5.1 DRC
6.5.2 XOR check
6.5.3 Antenna check
6.5.4 ERC
6.5.5 LVS check
6.6 Clock Network
6.7 Power Network
6.8 Engineering Change Order
6.9 Package
6.10 Summary
6.11 Problems
References
Chapter 7 Timing, Power, and Performance Analysis
7.1 Introduction
7.2 Buffer Insertion Mechanism
7.3 Transistor and Gate Sizing
7.3.1 Transistor sizing
7.3.2 Buffer sizing
7.3.3 Gate sizing
7.4 Timing Analysis
7.4.1 Static timing analysis
7.4.2 DTA vs. STA
7.4.3 Circuit simulation in STA
7.5 Interconnect Model and Circuit Order Reduction
7.5.1 Lumped RC vs. distributed RLC model
7.5.2 Circuit order reduction
7.6 Low Power Design
7.7 Design for Manufacture
7.8 High-level Synthesis
7.9 Performance Bound Evaluation
7.10 Summary
7.11 Problems
References
Chapter 8 Verification and Testing
8.1 Introduction
8.2 Digital Circuits Test
8.2.1 Fault modeling
8.2.2 Fault simulation
8.2.3 Test generation for combinational logic
8.2.4 Test generation for sequential logic
8.2.5 ATPG using TetraMAX
8.3 BIST
8.3.1 The concept of BIST
8.3.2 TPG
8.3.3 ORA
8.3.4 BIST architectures
8.4 Scan and Boundary Scan
8.4.1 Digital DFT for scan
8.4.2 Scan chains
8.4.3 Digital boundary scan standard- IEEE 1149.1
8.5 Summary
8.6 Problems
References
Appendix A A MSDAP
A.1 Introduction
A.2 A MSDAP
Appendix B A C-Program Implementing the Algorithm of the MSDAP
B.1 Introduction
B.2 The MSDAP Computation Method in C-Code
Appendix C An FSM for the MSDAP Operation Mode
C.1 Introduction
C.2 An FSM for the Operation Mode and System Setting
Appendix D A Sample Project MSDAP Report
D.1 Introduction
D.2 A Sample Project MSDAP Report
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